The present invention relates a static semiconductor memory device and. More particularly, the present invention to the cell structure of an improved CMOS static RAM and its fabrication method.
In general, a static random access memory (RAM) is widely used as a cache memory for computers or as a system memory for terminal equipment. Recently static RAMs that can be operated at high speed with low power consumption have been produced using large-scaled integration.
A static RAM that has a memory cell array comprising bistable flip-flop circuits is interior to a dynamic RAM in the integration of cells but it requires no periodic refresh operation, as needed in the dynamic RAM. Thus a static RAM does not employ refresh-related circuits. To accomplish low power consumption and large-scaled integration, a static RAM cell whose devices are all complementary metal-oxide-semiconductor (CMOS) transistors must use six MOS electric field effect transistors (FETs). One memory cell from the memory cell array comprises two driver transistors, two load transistors, and two switching transistors. Transistors of the same function are symmetrical to each other in terms of circuitry. The structure and function of a six transistor static memory cell is introduced in the second edition of the book "Semiconductor Memories" by B. Prince (pages 34 and 35), the contents of which are herein incorporated by reference.
FIG. 1 is a typical circuit diagram of a full CMOS static RAM comprising six transistors, first and second switching transistors Q.sub.T1 and Q.sub.T2, first and second driver transistors Q.sub.D1 and Q.sub.D2, and first and second load transistors Q.sub.L1 and Q.sub.L2 . The switching transistors Q.sub.T1 and Q.sub.T2 and the driver transistors Q.sub.D1 and Q.sub.D2 are n-channel MOSFETs, the load transistors Q.sub.L1 and Q.sub.L2 are p-channel MOSFETs. The static RAM cell is positioned at the intersection of the sets of complementary bit lines BL and BL* and word lines WL.sub.1, and WL.sub.2.
As shown in FIG. 1, the first and second switching transistors Q.sub.T1 and Q.sub.T2 connect the bit lines BL and BL* with the word lines WL.sub.1, and WL.sub.2. The source regions s.sub.T1 and s.sub.T2 of the first and second switching transistors Q.sub.T1 and Q.sub.T2 are respectively connected to the bitlines BL and BL*. The source regions s.sub.D1 and s.sub.D2 of the first and second driver transistors Q.sub.D1 and Q.sub.D2 are both connected to a ground wiring V.sub.ss. The source regions s.sub.L1, and s.sub.L2 of the first and second load transistors Q.sub.L1 and Q.sub.L2 are connected to a power supply wiring V.sub.cc. The drain regions d.sub.L1, d.sub.D1, and d.sub.T1, of the first load transistor Q.sub.L1, the first driver transistor Q.sub.D1 and the first switching transistor Q.sub.T1, respectively are connected together at a first node N.sub.1. The first node N.sub.1 is in turn connected to the gates of the second load transistor Q.sub.L2, and the second driver transistor Q.sub.D2. The drain regions d.sub.L2, d.sub.D2 and d.sub.T2, of the second load transistor Q.sub.L2, the second driver transistor Q.sub.D2 and the second switching transistor Q.sub.T2, respectively are connected together at a second node N.sub.2. The second node N.sub.2 is in turn connected to the gates of the first load transistor Q.sub.L1 and the first driver transistor Q.sub.D1.
The static RAM cell shown in FIG. 1 is undesirably large in size compared with a one-transistor dynamic RAM cell. In addition, the six-transistor static RAM cell has limitations in its fabrication and packing density because it must have interconnection layers between n-channel and p-channel transistors and gate connection layers for cross-couplings. These interconnection layers exist in the first and second nodes N.sub.1 and N.sub.2, in FIG. 1. For instance, the node N.sub.1 is connected to the drain regions d.sub.L1, d.sub.D1 and d.sub.T1. While the drain region d.sub.L1 is a p.sup.+ active region heavily doped with p-type ions, the drain region d.sub.D1, is an n.sup.+ active region.
In a method of fabricating a typical full CMOS memory cell, the isolation between a first n.sup.+ active region (r.sub.1) and a second n.sup.+ active region (r.sub.2) is made by a field oxide region in a substrate and connected to the gates that are opposite to each other by a separate conductive layer on the substrate. The conductive layer is an interconnection layer that is essential informing the first and second nodes N.sub.1, and N.sub.2. To provide complete nodes N.sub.1 and N.sub.2, it is necessary to connect the interconnection layer by the gates that are opposite to each other, in an additional process for forming a gate connection layer (cross-couplings).
A method of forming cross-couplings to solve these problems with the static RAM, cell such as difficulty in its fabrication and filling density, is disclosed in U.S. Pat. No. 4,740,479 under the title of "Method for the manufacture of cross-couplings between n-channel and p-channel CMOS field effect transistors of static write-read memories." In the disclosed method, a gate level comprising double polyside layers is used as an additional wiring level for forming the cross-couplings. To manufacture the cross-couplings, a field oxide layer is deposited by a known LOCOS method to defined an active region. After the gate oxide layer on the active region is photo-etched to open a buried contact, a double-layered structure of a polysilicon layer and a metal salicide layer is deposited and patterned to structure the gate electrode and cross-couplings shown in FIG. 1. As shown in FIG. 1, the gate of the second driver transistor Q.sub.D2 is connected to the drain region d.sub.L1 of the first load transistor Q.sub.L1 through the buried contact. The gate of the first driver transistor Q.sub.D1 is connected to the drain region d.sub.L2 of the second load transistor Q.sub.L2, through another buried contact.
In the above method, it is difficult to reduce the size of cell because each of the nodes N.sub.1, and N.sub.2 forms a connection through one contact. For example, when the gate of the second driver transistor Q.sub.D2 is connected to the drain region d.sub.L1 of the first load transistor Q.sub.L1 through one buried contact, the drain region d.sub.D1 of the first driver transistor Q.sub.D1 must be connected to the gate of the second driver transistor Q.sub.D2 through another buried contact.
Five buried contacts are thus required to form a complete connection between the nodes N.sub.1, and N.sub.2 in each cell, and this is a main factor for limiting the margin of design pattern. Furthermore, the integration of cells is hard to realize because a bird's beak of a field oxide layer occurs during the LOCOS process performed to separate the transistor devices.
In the prior art as described above, it must be noted that a double-layered structure of the polysilicon layer and the metal salicide layer are formed after photo-etching the gate oxide layer to open the buried contact. The interfacial characteristic between the gate oxide layer and the polysilicon layer deteriorates due to the particles and other contaminants produced during the etching process of the buried contact. Impurity ions are implanted to form source and drain regions accompanied by a diffusion (drive-in) process after an undoped polyside layer is deposited. Thus the resistance of the buried contact may be increased.
In the drive-in processing stage, the ions contained in tantalum salicide in the polyside layer are driven through the polysilicon layer across to the active region in the substrate having a buried contact. Since the polysilicon layer on the active region contains no impurity ions implanted, a part of the ions in the tantalum salicide remain in the polysilicon layer and only the rest ions are driven to the active region having the buried contact formed on it. Such an incomplete diffusion of impurity ions increases the resistance of the buried contact on the active region. The inferior interfacial characteristic and increased resistance in the contact result in the limitations of the static RAM cell's operation of high speed and low power consumption.